View STE110NA20_69702.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

STE110NA20
N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR
PRELIMINARY DATA TYPE ST E110NA20 V DSS 200 V R DS(on) < 0.019 ID 110 A
s s s s
s s
s s
s
TYPICAL RDS(on) = 0.015 HIGH CURRENT POWER MODULE AVALANCHE RUGGED TECHNOLOGY VERY LARGE SOA - LARGE PEAK POWER CAPABILITY EASY TO MOUNT SAME CURRENT CAPABILITY FOR THE TWO SOURCE TERMINALS EXTREMELY LOW Rth (Junction to case) VERY LOW INTERNAL PARASITIC INDUCTANCE ISOLATED PACKAGE UL RECOGNIZED
ISOTOP
APPLICATIONS s SMPS & UPS s MOTOR CONTROL s WELDING EQUIPMENT s OUTPUT STAGE FOR PWM, ULTRASONIC CIRCUITS
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol V DS V DGR V GS ID ID I DM (*) P to t Parameter Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k) Gate-source Voltage Drain Current (continuous) at Tc = 25 C Drain Current (continuous) at Tc = 100 C Drain Current (pulsed) Total Dissipation at T c = 25 C Derating Factor T st g Tj V ISO Storage Temperature Max. Operating Junction Temperature Insulation Withhstand Voltage (AC-RMS)
o o o
Value 200 200 30 110 73 440 450 3.6 -55 to 150 150 2500
Unit V V V A A A W W/ C
o o o
C C
V
(*) Pulse width limited by safe operating area
March 1996
1/8
STE110NA20
THERMAL DATA
R t hj-ca se R thc -h Thermal Resistance Junction-case Thermal Resistance Case-heats ink With Conductive Grease Applied Max Max 0.27 0.05
o
C/W C/W
o
AVALANCHE CHARACTERISTICS
Symb ol I AR E AS E AR I AR Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max, < 1%) Single Pulse Avalanche Energy (starting Tj = 25 oC, ID = I AR , V DD = 50 V) Repetitive Avalanche Energy (pulse width limited by Tj max, < 1%) Avalanche Current, Repetitive or Not-Repetitive (T c = 100 o C, pulse width limited by Tj max, < 1%) Max Valu e 55 500 175 32.5 Unit A mJ mJ A
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF
Symb ol V (BR)DSS I DSS I GSS Parameter Drain-source Breakdown Voltage I D = 1 mA Test Cond ition s V GS = 0 Min. 200 400 200 400 Typ . Max. Un it V A mA nA
V DS = Max Rating Zero Gate Voltage o Drain Current (V GS = 0) V DS = Max Rating x 0.8 T c = 125 C Gate-body Leakage Current (V DS = 0) V GS = 30 V
ON ()
Symb ol V GS(th) R DS( on) ID(o n) Parameter Gate T hreshold Voltage V DS = VGS Static Drain-source On Resistance On State Drain Current V GS = 10V V GS = 10V Test Cond ition s ID = 1 mA I D = 55 A ID = 55 A T c = 100 C 110
o
Min. 2.25
Typ . 3 0.015
Max. 3.75 0.019
Un it V A
V DS > I D(on) x R DS(on) max V GS = 10 V
DYNAMIC
Symb ol g fs () C iss C oss C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Cond ition s V DS =15 V V DS = 25 V f = 1 MHz ID = 55 A VGS = 0 Min. 38 12.9 2870 980 Typ . Max. Un it S nF pF pF
2/8
STE110NA20
ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symb ol t d(on) tr (di/dt) on Parameter Turn-on T ime Rise Time Turn-on Current Slope Test Cond ition s V DD = 100 V I D = 55 A VGS = 10 V R G = 4.7 (see test circuit, figure 3) V DD = 160 V I D = 110 A R G = 47 VGS = 10 V (see test circuit, figure 5) V DD = 160 V I D = 110 A V GS = 10 V Min. Typ . 70 95 290 Max. 100 125 Un it ns ns A/s
Qg Q gs Q gd
Total Gate Charge Gate-Source Charge Gate-Drain Charge
470 43 226
600
nC nC nC
SWITCHING OFF
Symb ol t r(Vof f) tf tc Parameter Off-voltage Rise Time Fall T ime Cross-over T ime Test Cond ition s V DD = 160 V ID = 110 A V GS = 10 V R G = 4.7 (see test circuit, figure 5) Min. Typ . 115 68 160 Max. 150 100 210 Un it ns ns ns
SOURCE DRAIN DIODE
Symb ol I SD I SDM (*) V SD () t rr Q rr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward O n Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 110 A V GS = 0 625 11 35 I SD = 110 A di/dt = 100 A/s o Tj = 150 C V R = 50 V (see test circuit, figure 5) Test Cond ition s Min. Typ . Max. 110 440 1.6 Un it A A V ns C A
() Pulsed: Pulse duration = 300 s, duty cycle 1.5 % (*) Pulse width limited by safe operating area
Safe Operating Area
Thermal Impedance
3/8
STE110NA20
Derating Curve Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
4/8
STE110NA20
Capacitance Variations Normalized Gate Threshold Voltage vs Temperature
Normalized On Resistance vs Temperature
Turn-on Current Slope
Turn-off Drain-source Voltage Slope
Cross-over Time
5/8
STE110NA20
Switching Safe Operating Area Accidental Overload Area
Source-drain Diode Forward Characteristics
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
6/8
STE110NA20
Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And DIode Recovery Times
7/8
STE110NA20
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersede and replaces all information previously supplied. s SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. (c) 1995 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A ...
8/8

▲Up To Search▲

Price & Availability of STE110NA20

	To Download STE110NA20 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .